1. Field of the Invention
The invention relates to a technique of chemical mechanical polishing of a substrate having non-flat shape with projected and recessed parts on the surface, particularly, a technique of chemically and mechanically polishing a silicon layer formed on a substrate so as to level the silicon layer. The invention is preferably applied to formation of a gate electrode and a contact plug formed of a leveled silicon layer.
2. Description of Related Art
An integrated circuit is generally formed on a substrate by continuous deposition of conductive, semiconductive, and insulating layers on a silicon wafer. After deposition of the respective layers, the respective layers are sometimes etched to provide circuit characteristics. To form a conductive path between thin film circuits, a step of the fabrication process may include formation of a plurality of via holes, plugs and lines. Further, to form electrodes with various shapes of thin film circuits, formation of a plurality of conductive units, for example, electrodes of a transistor and a capacitor is also included in a step of the fabrication process. These via holes, plugs, lines, electrodes and other conductive units can be formed by depositing a silicon layer such as a polycrystalline silicon (polysilicon or p-Si) layer on a patterned insulating layer and leveling the silicon layer by polishing or etching the silicon layer until the insulating layer is exposed. The portions of the silicon layer left between neighboring raised patterns of the insulating layer form the via holes, plugs, lines, electrodes and other conductive units.
A chemical mechanical polishing (CMP) method is one of commonly known methods of leveling a silicon layer or exposing an underlaid insulating layer using a polishing pad and a slurry. Effective CMP process provides a flat substrate surface without small-scale unevenness, large-scale topography or shape difference. In addition, the CMP process suppresses dishing (excess polishing of a silicon layer so as to make the silicon layer lower than the insulating layer) and corrosion (removal of the insulating layer) to the minimum.
In the case of a self-alignment FET device or the like, transistor electrodes or capacitor electrodes are formed by embedding a silicon layer in recessed parts of the substrate surface
Hereinafter, one example of conventional techniques for embedding the silicon layer in the recessed parts of the substrate surface and leveling the substrate surface will be described.
FIGS. 5A and 5B show a conventional leveling technique (see, e.g., JP-A 2002-518845). As shown in FIG. 5A, an insulating layer 15 of silicon oxide or the like is formed on a semiconductor layer 11 of a silicon wafer or the like. The insulating layer 15 is patterned or is formed on a patterned underlayer and thus made to have non-flat outer surface having projected and recessed parts. The insulating layer has a function as a stopper layer at the time of removing projected parts of the silicon layer in the step of chemically and mechanically polishing the silicon layer thereafter.
Further, over the entire face of the above-mentioned substrate, a polycrystalline silicon layer 13 is formed so as to cover the insulating layer 15. As illustrated, the outer surface of the polycrystalline silicon layer 13 reproduces the surface structure of the underlayer including the insulating layer 15 and form a series of recessed parts and projected parts so as to make the exposed face non-flat.
Next, using a polycrystalline silicon polishing slurry, the polycrystalline silicon layer 13 on the insulating layer is removed by chemical mechanical polishing. Accordingly, an embedded pattern of the polycrystalline silicon is formed in the recessed parts the insulating layer 15.
However, in this method, the polycrystalline silicon layer in the recessed parts of the substrate surface is exposed constantly to the polycrystalline silicon polishing slurry and a polishing pad. As shown in FIG. 5B, dishing of the silicon layer occurs to make the thickness of the embedded polycrystalline silicon layer uneven.
Particularly, in the case of a silicon layer pattern with 1 μm or larger in width, the dishing is significant. This excess polishing of the silicon layer makes the thickness of the embedded silicon layer to be wiring or electrodes uneven or eliminates the silicon layer regions to result in unevenness of the transistor characteristics and wiring resistance or electrode elimination or wiring disconnection and thus the process yield is lowered.